A charge trap memory may include charge trap memory cells, each having two or more transistors. The charge trap memory may be coupled to a sense circuit to generate outputs corresponding to the logical states of the charge trap memory cells during a read operation.
The logical state of a particular charge trap memory cell may be based on the respective states of its transistors. The transistors may be associated with respective voltage thresholds, and differences between the respective voltage thresholds may exist due to certain imperfections in manufacturing of the transistors. Prior to programming of the particular charge trap memory cell, the magnitudes of the differences in the voltage thresholds may be unknown and/or undetectable. Because the respective voltage thresholds correspond to the states of the transistors, and because their differences in magnitude are unknown prior to programming, the logical state of the particular charge trap memory cell is also unknown prior to programming. As a result, without a known logical state of the particular charge trap memory cell, testing the output of the sense circuit may be difficult.